1. Field
The present invention relates to a semiconductor memory device.
2. Description of the Related Art
Information that is stored in a memory cell of a semiconductor memory apparatus, such as a DRAM (Dynamic Random Access Memory), a FeRAM (Ferroelectric Random Access Memory), or the like, is read out from the memory cell at the time of a read-out operation and amplified by a latch-type sense amplifier circuit, and an amplified signal is output. A sense amplifier circuit, a precharge circuit, a column selection circuit, and the like are connected to the bit lines of the semiconductor memory apparatus (for example, see JP-A-8-287681).
In the read-out operation of the semiconductor memory apparatus described in JP-A-8-287681 or the like, a signal of a memory cell to be output to a bit line is determined by a ratio of capacitance of the memory cell and capacitance of the bit line. Parasitic capacitance of the memory cell, the sense amplifier circuit, the precharge circuit, the column selection circuit, and the like connected to the bit line may be regarded as bit line parasitic capacitance.
In recent years, with the development of miniaturization and high integration of a semiconductor device, the cell size of the memory cell is reduced, and cell capacitance becomes small. Meanwhile, with respect to bit line capacitance, even if the number of memory cells to be connected to the bit line decreases, parasitic capacitance of a circuit part, such as a sense amplifier circuit, a precharge circuit, a column selection circuit, and the like, remains as an offset. That is, while capacitance of the memory cell decreases due to miniaturization, it is difficult to decrease the bit line capacitance, as compared with capacitance of the memory cell. For this reason, with the development of miniaturization of the semiconductor device, the sense operation margin at the time of the read-out operation may be lowered. In addition, the sense speed at the time of the read-out operation may be lowered.